The present invention relates to fault detecting for information processing systems, or more in particular to a fault detecting apparatus for detecting an error and processing the detected error in microprocessors.
A high level of reliability is required for improved performance of a computer. In order to improve the reliability of the computer, it is necessary to detect an error accurately and to recover from the error without bringing the system down whenever an error occurs.
A method for detecting an error includes a parity check. This method, however, is not used widely as chip area increases thereby causing an increased chip cost and chip performance deterioration of the microprocessor.
A master checker scheme has been conceived as a method for detecting an error of a microprocessor. In the master checker scheme, two processors are operated synchronously and the outputs thereof are compared to detect an error, if any, thereby guaranteeing the data integrity. The use of the master checker scheme makes it possible to detect an error with the addition of comparatively small hardware.
Methods for error recovery include the automatic hardware recovery with reexecution of an instruction, the function clipping and a process succession using a multiprocessor.